ch7521a-利来app官网

general

lcompliant with displayport specification version 1.2 and embedded displayport (edp) specification version 1.2

lsupport vesa and cea timing standards up to 7680x1080@60hz or 4800x2160@60hz with 8/10 bit graphic color depth

lsupport single port, dual ports , quad ports and six ports lvds output interface

lcrystal free

lbuilt in self test mode support

lhot plug detection

lsupport dithering from 10 bit to 8 bit and 8-bit frc

lregion crc checking support

lblack panel or color bar during invalid input and failure detection

l15-pixel overlap on the left and right sides support, and enabled by the internal register

linitiated and controlled by firmware which is loaded from external boot rom automatically upon power up

lintegrated edid buffer up to 2 blocks

lfirmware updated through i2c slave or aux channel

li2c slave support up to 400k hz

lprogrammable power management

lachieve bit error rate <10-9 for raw transport data per lane and symbol error rate <10-12 for control data

llow power consumption

lesd hbm 4kv

loffered in a 128-pin qfn package (12.5 x 12.5mm)