ch7111a
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lcompliant with hdmi specification version 2.1 lsupports up to hdmi 12gbps frl data rate lsupports up to hdmi 6gbps tmds data rate or 600 mhz tmds clock for video transport ldedicated pll for removing the jitter of tmds clock and data, integrated cdr for removing the jitter of frl signal ldp support in ac coupling input mode for hdmi level shifter ldc coupling input mode support for hdmi signal retiming lautomatic link training for frl mode lscdc (status and control data channel) interception supported ladaptive equalizer to compensate for hdmi cables, pcb layout and/or connector losses, and supports up to 34 db boost at 600mhz lconfigurable pre-emphasis on output driver l3.3 and 1.2v power supply lcrystal-free liic-over-aux transaction supported lactive ddc buffer and related control register integrated lhdmi identifier supported liic serial port for configuration and chip debugging llow power architecture lrohs compliant and halogen free package lhbm 4kv esd performance loffered in 48-pin qfn package (6 x 6 mm)
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chrontel’s ch7111a is an
innovative, low-power, high performance hdmi re-timing semiconductor device for
improving the input tmds/frl signal to meet the hdmi 2.1 signal integrity
requirement. this device integrates adaptive equalizer, receiver cdr, internal
oscillator, high performance pll and configurable pre-emphasis module, and is
specially designed targeting for the hdmi 2.1 repeater and the dp adaptor
market segments.
pcb layout and design guide for ch7111a, an-b057 rev0.1
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