ch7512a
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nsupports displayport specification version 1.2 and embedded displayport (edp) specification version 1.4
nsupport 2 main link lanes at either 1.62gb/s, 2.7gb/s , 3.24gb/s or 5.4gb/s link rate
nsupports input color depth 6, 8-bit per pixel in rgb format
nsupports enhanced framing mode
nsupport vesa and cea timing standards up to 1920x1080 resolution in 8-bit input with 60hz refresh rate(1), or with 144hz refresh rate(2)
nsupport dynamic refresh rate switching
npanel tuning methods support 6-bit frc
nfast and full link training for displayport system
ncrystal free
nprogrammable lcd panel power sequence
nsupport 18-bit single port, 18-bit dual port, 24-bit single port and 24-bit dual port lvds output interface
nsupport both openldi and spwg bit mapping for lvds application
nsupport panel select by gpio pins control or writing the chip registers.
nflexible lvds output pins swapping
nblank panel during invalid input
ntest pattern generator integrated
nsupports pwm. backlight luminance level control through aux channel, pwm input pin and blup/bldn pin
nsupport osd display when blup/bldn pins control backlight luminance
nsupport chip power down control by gpio pin
nhot plug detection
nloads boot rom automatically upon power up
nserial boot rom data updated through i2c bus or aux channel
nsupport power management mechanism through aux channel
nemi reduction capability for dp input and lvds output. spread spectrum control is available for transmitting lvds signal
nlow power consumption
noffered in a 68-pin qfn package
nsupport pin to pin compatible with ch7511b*
chrontel’s ch7512a is a low-cost, low-power semiconductor device that translates the displayport signal to the lvds (low-voltage differential signaling). this innovative displayport receiver with an integrated lvds transmitter is specially designed to target the all-in-one pc and the notebook market segments. through the ch7512a’s advanced decoding / encoding algorithm, the input displayport high-speed serialized video data can be seamlessly converted to lvds, a popular display technology for high-speed serial links in mid/large-sized lcd displays. leveraging the displayport’s unique source/sink “link training” routine, the ch7512a is capable of instantly bring up the video display to the lcd when the initialization process is completed between ch7512a and the graphic chip.
the ch7512a is designed to meet the displayport specification 1.2 and embedded displayport (edp) specification version 1.4. in the device’s receiver block, which supports two displayport main link lanes input with data rate running at either 1.62gb/s, 2.7gb/s, 3.24gb/s or 5.4gb/s, can accept rgb digital formats in either 18-bit 6:6:6 or 24-bit 8:8:8 for lvds output up to 1920x1080@60hz(1) or 1920x1080@144hz(2). to comply with gpu’s new power saving scheme such as display frame rate reduction, the ch7512a is equipped with the dynamic refresh rate switching method, which can automatically reduce to the low refresh rate supported by the lvds panel.
the integrated lvds transmitter supports the single port and the dual ports lvds outputs. ch7512a supports panel select by gpio[5, 3:0] pins control. to reduce emi emission, the ch7512a’s lvds encoder block has incorporated spread spectrum control and its spread percentage can be adjusted through the internal registers.
the backlight on/off and the pwm are two luminance control functions designed in the ch7512a lvds power control module. the brightness control commands sent through aux channel can be dynamically translated by ch7512a and converted into lcd backlight control signal. the ch7512a will save the last setting of brightness level into the boot rom and restore it upon power up. the ch7512a can dynamically adjust backlight brightness according to video stream to save power consumption and it supports osd display in this way.
the ch7512a will immediately convert the displayport signal to lvds output after displayport link training is completed. this feature can be achieved by loading the panel’s edid and the ch7512a’s configuration settings in the serial boot rom connected to the ch7512a. during system power-up and upon completion of the displayport link training through aux channel, ch7512a will generate lvds signal according to the panel power-up timing sequencing stored in the boot rom. please contact chrontel for ch7512a’s firmware support.
pcb layout and design guide for ch7512a, an-b060 rev0.5
oct 2021
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