ch7516a-利来app官网

    advanced region crc checking and signal failure detection module and the related interrupt mechanism is incorporated in ch7516a, which is specially designed to reduce the risk of signal transmission error in normal consumer or industrial operation. " />

ch7516a

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特征

       lcompliant with displayport specification version 1.2 and embedded displayport (edp) specification version 1.4

       lsupport 4 main link lanes at either 1.62gb/s, 2.7gb/s , 3.24gb/s or 5.4gb/s link rate

       lsupport vesa and cea timing standards up to 7680x1080@60hz or 4800x2160@60hz with 8/10 bit graphic color depth

       lsupport single port, dual ports and quad ports lvds output interface

       lcrystal free

       l built in self test mode support

       lhot plug detection

       lpanel tuning methods support 8-bit frc

       lblack panel or color bar during invalid input and failure detection

       lintegrated edid buffer up to 2 blocks

       linitiated and controlled by firmware, which is loaded from external boot rom automatically upon power up

       lsupport boot rom with spi or i2c interface

       lfirmware updated through i2c slave or aux channel

       li2c slave support up to 400k hz

       lprogrammable power management

       lachieve bit error rate <10-9 for raw transport data per lane and symbol error rate <10-12 for control data

       llow power consumption

       lesd hbm 4kv

       loffered in a 128-pin qfn package (12.5 x 12.5mm)

描述

      chrontel’s ch7516a is a low-cost, low-power semiconductor device that translates the displayport signal to the lvds in form of rgb. this innovative displayport receiver with integrated 4 channel lvds transmitters is specially designed to target the aio and pc market segments. leveraging the displayport’s unique source/sink “link training” routine, the ch7516a is capable of instantly bring up the video display to the lcd when the initialization process is completed between ch7516a and the graphic chip.

the ch7516a is designed to meet the displayport specification version 1.2 and the embedded displayport specification version 1.4. the 4 main link lanes receiver supports input with data rate running at 1.62gb/s, 2.7gb/s, 3.24gb/s or 5.4gb/s, and can accept digital rgb signal for lvds output up to 7680x1080@60hz or 4800x2160@60hz.

     the ch7516a will convert the displayport signal to lvds output after displayport link training is completed. this feature can be achieved by loading the panel’s edid and the ch7516a’s configuration settings in the serial external boot rom connected to the ch7516a. during system power-up and upon completion of the displayport link training through aux channel, ch7516a will generate lvds signal according to the panel power-up timing sequencing stored in the external boot rom.

    advanced region crc checking and signal failure detection module and the related interrupt mechanism is incorporated in ch7516a, which is specially designed to reduce the risk of signal transmission error in normal consumer or industrial operation.

结构图

数据表

应用说明

 pcb layout and design guide for ch7516a, an-b061 rev0.1

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